How to write a test bench for vhdl code

--How to write a test bench for vhdl code
--here is a simple vhdl code for AND operation

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ex_testbench is
port(a,b,clk:in std_logic;c:out std_logic);
end ex_testbench;
architecture Behavioral of ex_testbench is
begin
process(clk,a,b)
begin
if clk'event and clk='1' then
c<=a and b;
end if;
end process;
end Behavioral;

 

Note: It's very important to write a  sensitivity list in process statement  otherwise program will not give any output...

 

--Testbench
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;

ENTITY test2 IS
END test2;

ARCHITECTURE behavior OF test2 IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT ex_testbench
    PORT(
         a : IN  std_logic;
         b : IN  std_logic;
         clk : IN  std_logic;
         c : OUT  std_logic
        );
    END COMPONENT;
--   
   --Inputs
   signal a : std_logic := '0';
   signal b : std_logic := '0';
   signal clk : std_logic := '0';
  --Outputs
   signal c : std_logic;
   -- Clock period definitions
   constant clk_period : time := 100 ns;

BEGIN

 -- Instantiate the Unit Under Test (UUT)
   uut: ex_testbench PORT MAP (
          a => a,
          b => b,
          clk => clk,
          c => c
        );
   -- Clock process definitions
   clk_process :process
   begin
  clk <= '0';
  wait for clk_period/2;
  clk <= '1';
  wait for clk_period/2;
  clk <= '0';
  wait for clk_period/2;
  clk <= '1';
  wait for clk_period/2;
   end process;

   -- Stimulus process
   stim_proc1: process
   begin

      a <= '0';
  wait for 10 ns;
  a<= '1';
  wait for 10 ns;

    
  if now>1000 ns then
  wait;
  end if;
   end process;

  stim_proc2: process
   begin
     
     
  b <= '1';
  wait for 10 ns;
  b<= '0';
  wait for 10 ns;


  if now>1000 ns then
  wait;
  end if;
   end process;
END;

 

--output