TO DESIGN AND
SIMULATE DATA PATH FOR PERFORMING A=A+3 AND A=B+C USING ONLY ONE ADDER.
--CODE FOR ADD_PATH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ADD_PATH is
Port ( IN1,IN2 : in STD_LOGIC_VECTOR (07 downto 0);
OUTT : out STD_LOGIC_VECTOR (07 downto 0));
end ADD_PATH;
architecture Behavioral of
ADD_PATH is
begin
OUTT<= IN1 + IN2;
end Behavioral;
--CODE FOR REG_PATH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity REG_PATH is
Port ( DIN : in STD_LOGIC_VECTOR (07 downto
0):="00000000";
CLK : in STD_LOGIC;
RESETT : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (07 downto 0));
end REG_PATH;
architecture Behavioral of
REG_PATH is
begin
process(CLK,RESETT,DIN)
begin
if RESETT = '1' then
DOUT <=
"00000000";
elsif CLK'event and CLK = '1'
then
DOUT <= DIN;
else
null;
end if;
end process;
end Behavioral;
--CODE FOR MUX_PATH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX_PATH is
Port ( IN1,IN2 : in STD_LOGIC_VECTOR (07 downto 0);
SEL : in STD_LOGIC;
OUTT : out STD_LOGIC_VECTOR (07 downto 0));
end MUX_PATH;
architecture Behavioral of
MUX_PATH is
begin
PROCESS(IN1,IN2,SEL)
BEGIN
IF SEL='1' THEN OUTT<=
IN1;
ELSE OUTT<=IN2;
END IF;
END PROCESS;
end Behavioral;
--CODE FOR CONSTANT_PATH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CONSTANT_PATH is
Port ( A : in STD_LOGIC_VECTOR (07 downto 0);
B : out STD_LOGIC_VECTOR (07 downto 0));
end CONSTANT_PATH;
architecture Behavioral of
CONSTANT_PATH is
begin
B<=A;
end Behavioral;
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