VHDL code for BCD adder

--vhdl code for BCD adder

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

ENTITY NAND_GATE IS

PORT(A,B:IN STD_LOGIC;C:OUT STD_LOGIC);

END NAND_GATE;

ARCHITECTURE NAND_ARCH OF NAND_GATE IS

BEGIN

C<=(NOT(A AND B));

END NAND_ARCH;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY HALF_ADDER IS

PORT(A,B:IN STD_LOGIC;SUM,CARRY:OUT STD_LOGIC);

END HALF_ADDER;

ARCHITECTURE HALF_ADDER_ARCH OF HALF_ADDER IS

SIGNAL X1,X2,X3:STD_LOGIC;

COMPONENT NAND_GATE

PORT(A,B:IN STD_LOGIC;C:OUT STD_LOGIC);

END COMPONENT;

BEGIN

STEP1:NAND_GATE PORT MAP (A,B,X1);

STEP2:NAND_GATE PORT MAP (A,X1,X2);

STEP3:NAND_GATE PORT MAP (B,X1,X3);

STEP4:NAND_GATE PORT MAP (X2,X3,SUM);

CARRY<=((A NAND B)NAND (A NAND B));

END HALF_ADDER_ARCH;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY BITFULLADDER IS

PORT(A,B,CIN:IN STD_LOGIC;SUM,CARRY:OUT STD_LOGIC);

END BITFULLADDER;

ARCHITECTURE BITFULLADDER_ARCH OF BITFULLADDER IS

COMPONENT HALF_ADDER

PORT(A,B:IN STD_LOGIC;SUM,CARRY:OUT STD_LOGIC);

END COMPONENT;

SIGNAL Z1,C1,C2: STD_LOGIC;

BEGIN

STEP5:HALF_ADDER PORT MAP(A,B,Z1,C1);

STEP6:HALF_ADDER PORT MAP(CIN,Z1,SUM,C2);

CARRY<=((C1 NAND C1) NAND (C2 NAND C2));

END BITFULLADDER_ARCH;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

entity BIT4fulladder is

    Port ( A0,A1,A2,A3,B0,B1,B2,B3 : in  STD_LOGIC;

           CIN : in  STD_LOGIC;

           S0,S1,S2,S3 : out  STD_LOGIC;

           CARRY : out  STD_LOGIC);

end BIT4fulladder;

architecture Behavioral of BIT4fulladder is

SIGNAL C1,C2,C3:STD_LOGIC;

COMPONENT BITFULLADDER

PORT(A,B,CIN:IN STD_LOGIC;SUM,CARRY:OUT STD_LOGIC);

END COMPONENT;

begin

STEP7:BITFULLADDER PORT MAP(A0,B0,CIN,S0,C1);

STEP8:BITFULLADDER PORT MAP(A1,B1,C1,S1,C2);

STEP9:BITFULLADDER PORT MAP(A2,B2,C2,S2,C3);

STEP10:BITFULLADDER PORT MAP(A3,B3,C3,S3,CARRY);

end Behavioral;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY XOR1 IS

PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC);

END XOR1;

ARCHITECTURE XOR1_ARCH OF XOR1 IS

COMPONENT NAND_GATE

PORT(A,B:IN STD_LOGIC;C:OUT STD_LOGIC);

END COMPONENT;

SIGNAL X1,X2,X3:STD_LOGIC;

BEGIN

STEP17:NAND_GATE PORT MAP (A,B,X1);

STEP18:NAND_GATE PORT MAP (A,X1,X2);

STEP19:NAND_GATE PORT MAP (B,X1,X3);

STEP20:NAND_GATE PORT MAP (X2,X3,C);

END XOR1_ARCH;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY BCD_4BIT_ADDER IS

PORT(A0,A1,A2,A3,B0,B1,B2,B3:IN STD_LOGIC;

     CIN:IN STD_LOGIC;S0,S1,S2,S3:OUT STD_LOGIC;

       CARRY:OUT STD_LOGIC);

END BCD_4BIT_ADDER;

ARCHITECTURE BCD_4BIT_ADDER_ARCH OF BCD_4BIT_ADDER IS

COMPONENT BITFULLADDER

PORT(A,B,CIN:IN STD_LOGIC;SUM,CARRY:OUT STD_LOGIC);

END COMPONENT;

COMPONENT XOR1

PORT(A,B:IN STD_LOGIC; C:OUT STD_LOGIC);

END COMPONENT;

SIGNAL J0,J1,J2,J3,C1,C2,C3,C4,C5,C6,CR: STD_LOGIC;

BEGIN

STEP11:BITFULLADDER PORT MAP(A0,B0,CIN,J0,C1);

STEP12:BITFULLADDER PORT MAP(A1,B1,C1,J1,C2);

STEP13:BITFULLADDER PORT MAP(A2,B2,C2,J2,C3);

STEP14:BITFULLADDER PORT MAP(A3,B3,C3,J3,C4);

CR<=(((J3 NAND J2)NAND(J3 NAND J1)) NAND ((C4 NAND C4)));

S0<=J0;

STEP15:BITFULLADDER PORT MAP(J1,CR,'0',S1,C5);

STEP16:BITFULLADDER PORT MAP(J2,CR,'0',S2,C6);

STEP21: XOR1 PORT MAP(J3,C6,S3);

CARRY<=CR;

END BCD_4BIT_ADDER_ARCH;