VHDL code for multiplexer

--4 to 1 multiplexer

library IEEE;
use IEEE.std_logic_1164.all;

entity mux is
generic(N :integer := 4);
port ( a,b,c,d: in STD_LOGIC_VECTOR (N-1 downto 0);
sel: in STD_LOGIC_VECTOR(1 downto 0); o: out STD_LOGIC_VECTOR (N-1 downto 0));
end mux;

architecture mux_arch of mux is

begin
process (sel, a, b, c, d)
begin

case sel is
when "00"  => o  <= a;
when "01"  => o  <= b;
when "10"  => o  <= c;
when others => o  <= d;
end case;
end process;

end mux_arch;