VHDL code for Ring Counter

 

 

 

Ring Counter VHDL code

 

--Ring counter
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
entity Ring_counter is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           output : out  STD_LOGIC_VECTOR (3 downto 0));
end Ring_counter;
architecture Behavioral of Ring_counter is
signal temp : STD_LOGIC_VECTOR(3 downto 0):=(others => '0');
begin
process(clk)
begin
    if( clk'event and clk='1' ) then
        if (reset = '1') then
            temp <= (0=> '1', others => '0');
        else
            temp(1) <= temp(0);
            temp(2) <= temp(1);
            temp(3) <= temp(2);
            temp(0) <= temp(3);
        end if;
    end if;
end process;
output<=temp;
end Behavioral;



--Testbench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY testbench_r_counter IS
END testbench_r_counter;

ARCHITECTURE behavior OF testbench_r_counter IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT Ring_counter
    PORT(
         clk : IN  std_logic;
         reset : IN  std_logic;
         output : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
   
   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
  --Outputs
   signal output : std_logic_vector(3 downto 0);
   -- Clock period definitions
   constant clk_period : time := 10 ns;

BEGIN

 -- Instantiate the Unit Under Test (UUT)
   uut: Ring_counter PORT MAP (
          clk => clk,
          reset => reset,
          output => output
        );
   -- Clock process definitions
   clk_process :process
   begin
  clk <= '0';
  wait for clk_period/2;
  clk <= '1';
  wait for clk_period/2;
   end process;

   -- Stimulus process
   stim_proc: process
   begin
    
reset<='1';
wait for 10 ns;
reset<='0';
wait;
  end process;
END behavior;



--output