How to use function in VHDL code

How to use function in VHDL code


-----------------------main code-------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
use IEEE.STD_LOGIC_arith.ALL;
library work;
use work.arith.all;

entity addition is
    Port ( a : in  STD_LOGIC_vector(3 downto 0);
           b : in  STD_LOGIC_vector(3 downto 0);
           c : out  STD_LOGIC_vector(3 downto 0));
end addition;

architecture Behavioral of addition is

begin
c<=add(a,b);

end Behavioral;

------------------------------------- package with function----------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

package arith is
function add(a1,b1: std_logic_vector) return std_logic_vector;
end arith;

package body arith is
function add(a1,b1: std_logic_vector) return std_logic_vector is
variable c1:std_logic_vector(3 downto 0);
begin
c1:=a1+b1;
return c1;
end add;
end arith;

--------------------------------------------------- Test bench------------------------------------------


LIBRARY ieee;
USE ieee.std_logic_1164.ALL;


ENTITY t3 IS
END t3;

ARCHITECTURE behavior OF t3 IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT addition
    PORT(
         a : IN  std_logic_vector(3 downto 0);
         b : IN  std_logic_vector(3 downto 0);
         c : OUT  std_logic_vector(3 downto 0)
        );
    END COMPONENT;
   

   --Inputs
   signal a : std_logic_vector(3 downto 0) := (others => '0');
   signal b : std_logic_vector(3 downto 0) := (others => '0');

     --Outputs
   signal c : std_logic_vector(3 downto 0);

BEGIN

    -- Instantiate the Unit Under Test (UUT)
   uut: addition PORT MAP (
          a => a,
          b => b,
          c => c
        );


   stim_proc: process
   begin       
      wait for 100 ns;   
a<= "0000";
b<="0000";
      wait for 100 ns;
        a<= "0010";
b<="0000";
  wait for 200 ns;
        a<= "0010";
b<="0100";
     
      wait;
   end process;

END;
------------------------------------------output--------------------------------------------------

 

Project file here

 Click here to Download