VHDL code for ALU

--vhdl code for ALU

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

LIBRARY ALU_LIB;

USE ALU_LIB.NAND_GATE_PACK.ALL;

USE ALU_LIB.XOR_GATE_PACK.ALL;

USE ALU_LIB.HALF_ADDER_PACK.ALL;

USE ALU_LIB.BITFULLADDER_PACK.ALL;

USE ALU_LIB.BIT4FULLADDER_PACK.ALL;

USE ALU_LIB.MULTIPLIERR_PACK.ALL;

USE ALU_LIB.TYPEE.ALL;

USE ALU_LIB.SUB_PACK.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity ALU is

    Port ( A : in  STD_LOGIC_VECTOR (03 downto 0);

           B : in  STD_LOGIC_VECTOR (03 downto 0);

           CIN : in  STD_LOGIC;

           CARRY : out  STD_LOGIC;

                                                  SELECT_OP: IN STD_LOGIC_VECTOR(1 DOWNTO 0);

           OUTPUT : out  STD_LOGIC_VECTOR (07 downto 0));

end ALU;

architecture Behavioral of ALU is

SIGNAL C1,C2,C3,C4,S,M:STD_LOGIC;

SIGNAL J,K:STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL H:STD_LOGIC_VECTOR(7 DOWNTO 0);

begin

PROCESS(C1,C2,C3,C4,J,K,H,A,B,CIN,SELECT_OP,S,M)

BEGIN

IF SELECT_OP="00"--ADDITION

THEN OUTPUT<="000"&C4&J;

     CARRY<=C4;

ELSIF SELECT_OP="01"--SUBTRACTION

THEN OUTPUT<="0000"&K ;

     CARRY<=S;

ELSIF SELECT_OP="10"--MULTIPLICATION

THEN OUTPUT<=H ;

CARRY<=M;

ELSE NULL;

END IF;

END PROCESS;

ADDITION1:BITFULLADDER PORT MAP(A(0),B(0),CIN,J(0),C1);

ADDITION2:BITFULLADDER PORT MAP(A(1),B(1),C1,J(1),C2);

ADDITION3:BITFULLADDER PORT MAP(A(2),B(2),C2,J(2),C3);

ADDITION4:BITFULLADDER PORT MAP(A(3),B(3),C3,J(3),C4);

SUBTRACTION1:SUB PORT MAP(A,B,'0',K,S);

MULTIPLIER1:MULTIPLIERR PORT MAP(A,B,H,M);

end Behavioral; 

output: