Verilog: 4 Bit adder

//code top module
module adder4bit(a,b,cin,sum,carry);
output [3:0]sum;
output carry;
input [3:0]a;
input[3:0]b;
input cin;
wire w1,w2,w3;

full_adder x1(a[0],b[0],cin,sum[0],w1);
full_adder x2(a[1],b[1],w1,sum[1],w2);
full_adder x3(a[2],b[2],w2,sum[2],w3);
full_adder x4(a[3],b[3],w3,sum[3],carry);

endmodule

//code module
module full_adder( a,b,cin,sum,carry); // fulladder
output sum,carry;
input a,b,cin;
wire sum,carry;

wire w1,w2,w3;

assign sum=(a ^ b ^cin);
assign carry= ((a & b) | (a & cin) |(b & cin));

endmodule





//Testbench
`timescale 1ns / 1ps

module test1;

    // Inputs
    reg [3:0] a;
    reg [3:0] b;
    reg cin;

    // Outputs
    wire [3:0] sum;
    wire  carry;

    // Instantiate the Unit Under Test (UUT)
    adder4bit uut (
        .a(a),
        .b(b),
        .cin(cin),
        .sum(sum),
        .carry(carry)
    );

    initial begin
        // Initialize Inputs
        a = 0;
        b = 0;
        cin = 0;

        // Wait 100 ns for global reset to finish
        #100;
        a=4'b0001;
          b=4'b0010;
          cin=1'b0;
         
          #100;
        a=4'b1001;
          b=4'b0010;
          cin=1'b1;
          
          #100;
        a=4'b1001;
          b=4'b1010;
          cin=1'b0;
        // Add stimulus here

    end
     
endmodule



//Output