VHDL code for general datapath

--To Design and to simulate  a simple general data path circuit .
--ALU CODE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ALU is
    Port ( A : in  STD_LOGIC_VECTOR (07 downto 0);
           B : in  STD_LOGIC_VECTOR (07 downto 0);
           C : out  STD_LOGIC_VECTOR (07 downto 0);
           ALU2,ALU1,ALU0 : in  STD_LOGIC);
end ALU;
architecture Behavioral of ALU is
begin
PROCESS(A,B,ALU2,ALU1,ALU0)
BEGIN
IF (ALU2 & ALU1 & ALU0 ="000") THEN C<=A;
ELSIF (ALU2 & ALU1 & ALU0 ="001") THEN C<=A AND B;
ELSIF (ALU2 & ALU1 & ALU0 ="010") THEN C<=A OR B;
ELSIF (ALU2 & ALU1 & ALU0 ="011") THEN C<=NOT A;
ELSIF (ALU2 & ALU1 & ALU0 ="100") THEN C<=A + B;
ELSIF (ALU2 & ALU1 & ALU0 ="101") THEN C<=A - B;
ELSIF (ALU2 & ALU1 & ALU0 ="110") THEN C<=A + 1;
ELSE C<=A - 1;
END IF;
END PROCESS;
 end Behavioral;

--CODE FOR REG_PATH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity REG_PATH is
    Port ( DIN : in  STD_LOGIC_VECTOR (07 downto 0):="00000000";
           CLK : in  STD_LOGIC;
           RESETT : in  STD_LOGIC;
           DOUT : out  STD_LOGIC_VECTOR (07 downto 0):="00000000");
end REG_PATH;
architecture Behavioral of REG_PATH is
begin
process(CLK,RESETT,DIN)
begin
if RESETT = '1' then
DOUT <= "00000000";
elsif CLK'event and CLK = '1' then
DOUT <= DIN;
else
null;
end if;
end process;
end Behavioral;

--CODE FOR MUX_PATH
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX_PATH is
    Port ( IN1,IN2 : in  STD_LOGIC_VECTOR (07 downto 0);
           SEL : in  STD_LOGIC;
           OUTT : out  STD_LOGIC_VECTOR (07 downto 0));
end MUX_PATH;
architecture Behavioral of MUX_PATH is
begin
PROCESS(IN1,IN2,SEL)
BEGIN
IF SEL='1' THEN OUTT<= IN1;
ELSE OUTT<=IN2;
END IF;
END PROCESS;
end Behavioral;

--CODE FOR DATA_PATH_GENERAL
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity DATA_PATH_GENERAL is
   port ( CLK        : in    std_logic;
          CONSTANT_1 : in    std_logic_vector (7 downto 0);
          DATA_INN   : in    std_logic_vector (7 downto 0);
          OP_0       : in    std_logic;
          OP_1       : in    std_logic;
          OP_2       : in    std_logic;
          RESETT     : in    std_logic;
          SELECTT    : in    std_logic;
          RESULT     : out   std_logic_vector (7 downto 0));
end DATA_PATH_GENERAL;
architecture BEHAVIORAL of DATA_PATH_GENERAL is
   signal XLXN_1       : std_logic_vector (7 downto 0);
   signal XLXN_2       : std_logic_vector (7 downto 0);
   signal RESULT_DUMMY : std_logic_vector (7 downto 0);
   component ALU
      port ( ALU2 : in    std_logic;
             ALU1 : in    std_logic;
             ALU0 : in    std_logic;
             A    : in    std_logic_vector (7 downto 0);
             B    : in    std_logic_vector (7 downto 0);
             C    : out   std_logic_vector (7 downto 0));
   end component;
  
   component REG_PATH
      port ( CLK    : in    std_logic;
             RESETT : in    std_logic;
             DIN    : in    std_logic_vector (7 downto 0);
             DOUT   : out   std_logic_vector (7 downto 0));
   end component;
  
   component MUX_PATH
      port ( SEL  : in    std_logic;
             IN1  : in    std_logic_vector (7 downto 0);
             IN2  : in    std_logic_vector (7 downto 0);
             OUTT : out   std_logic_vector (7 downto 0));
   end component;
  
begin
   RESULT(7 downto 0) <= RESULT_DUMMY(7 downto 0);
   XLXI_1 : ALU
      port map (A(7 downto 0)=>XLXN_1(7 downto 0),
                ALU0=>OP_0,
                ALU1=>OP_1,
                ALU2=>OP_2,
                B(7 downto 0)=>RESULT_DUMMY(7 downto 0),
                C(7 downto 0)=>XLXN_2(7 downto 0));
  
   XLXI_2 : REG_PATH
      port map (CLK=>CLK,
                DIN(7 downto 0)=>XLXN_2(7 downto 0),
                RESETT=>RESETT,
                DOUT(7 downto 0)=>RESULT_DUMMY(7 downto 0));
  
   XLXI_4 : MUX_PATH
      port map (IN1(7 downto 0)=>DATA_INN(7 downto 0),
                IN2(7 downto 0)=>CONSTANT_1(7 downto 0),
                SEL=>SELECTT,
                OUTT(7 downto 0)=>XLXN_1(7 downto 0));
   end BEHAVIORAL;



--SCHEMATIC OF DATA_PATH_GENERAL

--OUTPUT OF SHEMATIC