--CODE FOR T_PATH
library
IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity
T_PATH is
Port ( T : in STD_LOGIC;
CLK : in STD_LOGIC;
RESETT : in STD_LOGIC;
Q : INout STD_LOGIC:='0';
QBAR : out STD_LOGIC);
end
T_PATH;
architecture
Behavioral of T_PATH is
begin
process(clk,T,RESETT)
begin
IF
RESETT='1' THEN Q<='0';
ELSif
(clk' event and clk='1') then
if(t='1')
then
q<=
not (q);
QBAR<=Q;
else
q<=q;
QBAR<=
NOT Q;
end
if;
end
if;
end
process;
end
Behavioral;
--CODE FOR DOWN_COUNTER
library
ieee;
use
ieee.std_logic_1164.ALL;
use
ieee.numeric_std.ALL;
entity
DOWN_COUNTER is
port ( CLK : in
std_logic;
LOGIC_1 : in std_logic;
RESETT : in
std_logic;
Q_0 : inout std_logic;
Q_1 : inout std_logic;
Q_2 : inout std_logic;
Q_3 : inout std_logic);
end
DOWN_COUNTER;
architecture
BEHAVIORAL of DOWN_COUNTER is
component T_PATH
port ( T : in
std_logic;
CLK : in
std_logic;
RESETT : in std_logic;
Q : inout std_logic;
QBAR : out
std_logic);
end component;
begin
XLXI_1 : T_PATH
port map (CLK=>CLK,
RESETT=>RESETT,
T=>LOGIC_1,
QBAR=>open,
Q=>Q_0);
XLXI_2 : T_PATH
port map (CLK=>Q_0,
RESETT=>RESETT,
T=>LOGIC_1,
QBAR=>open,
Q=>Q_1);
XLXI_3 : T_PATH
port map (CLK=>Q_1,
RESETT=>RESETT,
T=>LOGIC_1,
QBAR=>open,
Q=>Q_2);
XLXI_4 : T_PATH
port map (CLK=>Q_2,
RESETT=>RESETT,
T=>LOGIC_1,
QBAR=>open,
Q=>Q_3);
end
BEHAVIORAL;
--CODE FOR DOWN_COUNTER8BIT
library
ieee;
use
ieee.std_logic_1164.ALL;
use
ieee.numeric_std.ALL;
entity
DOWN_COUNTER_8BIT is
port ( CLK : in
std_logic;
LOGIC_1 : in std_logic;
RESETT : in
std_logic;
Q_0 : inout std_logic;
Q_1 : inout std_logic;
Q_2 : inout std_logic;
Q_3 : inout std_logic;
Q_4 : inout std_logic;
Q_5 : inout std_logic;
Q_6 : inout std_logic;
Q_7 : inout std_logic);
end
DOWN_COUNTER_8BIT;
architecture
BEHAVIORAL of DOWN_COUNTER_8BIT is
component DOWN_COUNTER
port ( LOGIC_1 : in std_logic;
RESETT : in
std_logic;
CLK : in
std_logic;
Q_0 : inout std_logic;
Q_1 : inout std_logic;
Q_2 : inout std_logic;
Q_3 : inout std_logic);
end component;
begin
XLXI_1 : DOWN_COUNTER
port map (CLK=>CLK,
LOGIC_1=>LOGIC_1,
RESETT=>RESETT,
Q_0=>Q_0,
Q_1=>Q_1,
Q_2=>Q_2,
Q_3=>Q_3);
XLXI_2 : DOWN_COUNTER
port map (CLK=>Q_3,
LOGIC_1=>LOGIC_1,
RESETT=>RESETT,
Q_0=>Q_4,
Q_1=>Q_5,
Q_2=>Q_6,
Q_3=>Q_7);
end
BEHAVIORAL;
--CODE FOR VECTOR_PATH
library
IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity
VECTOR_PATH is
Port ( A0,A1,A2,A3,A4,A5,A6,A7 : in STD_LOGIC;
B : out
STD_LOGIC_VECTOR (07 downto 0));
end
VECTOR_PATH;
architecture
Behavioral of VECTOR_PATH is
begin
B(0)<=A0;
B(1)<=A1;
B(2)<=A2;
B(3)<=A3;
B(4)<=A4;
B(5)<=A5;
B(6)<=A6;
B(7)<=A7;
end
Behavioral;
--CODE FOR BITFULLADDER
library
IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
ENTITY
NAND_GATE IS
PORT(A,B:IN
STD_LOGIC;C:OUT STD_LOGIC);
END
NAND_GATE;
ARCHITECTURE
NAND_ARCH OF NAND_GATE IS
BEGIN
C<=(NOT(A
AND B));
END
NAND_ARCH;
LIBRARY
IEEE;
USE
IEEE.STD_LOGIC_1164.ALL;
ENTITY
HALF_ADDER IS
PORT(A,B:IN
STD_LOGIC;SUM,CARRY:OUT STD_LOGIC);
END
HALF_ADDER;
ARCHITECTURE
HALF_ADDER_ARCH OF HALF_ADDER IS
SIGNAL
X1,X2,X3:STD_LOGIC;
COMPONENT
NAND_GATE
PORT(A,B:IN
STD_LOGIC;C:OUT STD_LOGIC);
END
COMPONENT;
BEGIN
STEP1:NAND_GATE
PORT MAP (A,B,X1);
STEP2:NAND_GATE
PORT MAP (A,X1,X2);
STEP3:NAND_GATE
PORT MAP (B,X1,X3);
STEP4:NAND_GATE
PORT MAP (X2,X3,SUM);
CARRY<=((A
NAND B)NAND (A NAND B));
END
HALF_ADDER_ARCH;
LIBRARY
IEEE;
USE
IEEE.STD_LOGIC_1164.ALL;
ENTITY
BITFULLADDER IS
PORT(A,B,CIN:IN
STD_LOGIC;SUM,CARRY:OUT STD_LOGIC);
END
BITFULLADDER;
ARCHITECTURE
BITFULLADDER_ARCH OF BITFULLADDER IS
COMPONENT
HALF_ADDER
PORT(A,B:IN
STD_LOGIC;SUM,CARRY:OUT STD_LOGIC);
END
COMPONENT;
SIGNAL
Z1,C1,C2: STD_LOGIC;
BEGIN
STEP5:HALF_ADDER
PORT MAP(A,B,Z1,C1);
STEP6:HALF_ADDER
PORT MAP(CIN,Z1,SUM,C2);
CARRY<=((C1
NAND C1) NAND (C2 NAND C2));
END
BITFULLADDER_ARCH;
library
IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_ARITH.ALL;
use
IEEE.STD_LOGIC_UNSIGNED.ALL;
entity
BIT4FULLADDER is
Port ( A0,A1,A2,A3,B0,B1,B2,B3 : in STD_LOGIC;
CIN : in STD_LOGIC;
S0,S1,S2,S3 : out STD_LOGIC;
CARRY : out STD_LOGIC);
end
BIT4FULLADDER;
architecture
Behavioral of BIT4FULLADDER is
SIGNAL
C1,C2,C3:STD_LOGIC;
COMPONENT
BITFULLADDER
PORT(A,B,CIN:IN
STD_LOGIC;SUM,CARRY:OUT STD_LOGIC);
END
COMPONENT;
begin
STEP7:BITFULLADDER
PORT MAP(A0,B0,CIN,S0,C1);
STEP8:BITFULLADDER
PORT MAP(A1,B1,C1,S1,C2);
STEP9:BITFULLADDER
PORT MAP(A2,B2,C2,S2,C3);
STEP10:BITFULLADDER
PORT MAP(A3,B3,C3,S3,CARRY);
end
Behavioral;
--CODE FOR
ADDER8BIT
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
entity ADDER8BIT is
port ( CIN_0 :
in std_logic;
IN_01 :
in std_logic_vector (7 downto 0);
IN_02 :
in std_logic_vector (7 downto 0);
CARRY :
out std_logic;
OUT_1 :
out std_logic_vector (7 downto 0));
end ADDER8BIT;
architecture BEHAVIORAL of ADDER8BIT is
signal XLXN_1 : std_logic;
signal XLXN_2 : std_logic;
signal XLXN_3 : std_logic;
signal XLXN_4 : std_logic;
signal XLXN_5 : std_logic;
signal XLXN_6 : std_logic;
signal XLXN_7 : std_logic;
signal XLXN_8 : std_logic;
signal XLXN_9 : std_logic;
signal XLXN_10 :
std_logic;
signal XLXN_11 :
std_logic;
signal XLXN_12 :
std_logic;
signal XLXN_13 :
std_logic;
signal XLXN_15 :
std_logic;
signal XLXN_16 :
std_logic;
signal XLXN_17 :
std_logic;
signal XLXN_18 :
std_logic;
signal XLXN_23 :
std_logic;
signal XLXN_24 :
std_logic;
signal XLXN_25 :
std_logic;
signal XLXN_26 :
std_logic;
signal XLXN_27 :
std_logic;
signal XLXN_28 :
std_logic;
signal XLXN_29 :
std_logic;
signal XLXN_30 :
std_logic;
component
BIT4FULLADDER
port ( A0 : in
std_logic;
A1 : in
std_logic;
A2 : in
std_logic;
A3 : in
std_logic;
B0 : in
std_logic;
B1 : in
std_logic;
B2 : in
std_logic;
B3 : in
std_logic;
CIN : in
std_logic;
S0 : out
std_logic;
S1 : out
std_logic;
S2 : out
std_logic;
S3 :
out std_logic;
CARRY :
out std_logic);
end component;
component BOX_2
port ( A : in
std_logic_vector (7 downto 0);
B0 :
out std_logic;
B1 :
out std_logic;
B2 :
out std_logic;
B3 :
out std_logic;
B4 :
out std_logic;
B5 :
out std_logic;
B6 :
out std_logic;
B7 :
out std_logic);
end component;
component
VECTOR_PATH
port ( A0 :
in std_logic;
A1 :
in std_logic;
A2 :
in std_logic;
A3 :
in std_logic;
A4 :
in std_logic;
A5 :
in std_logic;
A6 :
in std_logic;
A7 : in std_logic;
B : out
std_logic_vector (7 downto 0));
end component;
begin
XLXI_1 :
BIT4FULLADDER
port map
(A0=>XLXN_2,
A1=>XLXN_3,
A2=>XLXN_4,
A3=>XLXN_5,
B0=>XLXN_10,
B1=>XLXN_11,
B2=>XLXN_12,
B3=>XLXN_13,
CIN=>CIN_0,
CARRY=>XLXN_1,
S0=>XLXN_23,
S1=>XLXN_24,
S2=>XLXN_25,
S3=>XLXN_26);
XLXI_2 :
BIT4FULLADDER
port map
(A0=>XLXN_6,
A1=>XLXN_7,
A2=>XLXN_8,
A3=>XLXN_9,
B0=>XLXN_15,
B1=>XLXN_16,
B2=>XLXN_17,
B3=>XLXN_18,
CIN=>XLXN_1,
CARRY=>CARRY,
S0=>XLXN_27,
S1=>XLXN_28,
S2=>XLXN_29,
S3=>XLXN_30);
XLXI_8 : BOX_2
port map (A(7
downto 0)=>IN_01(7 downto 0),
B0=>XLXN_2,
B1=>XLXN_3,
B2=>XLXN_4,
B3=>XLXN_5,
B4=>XLXN_6,
B5=>XLXN_7,
B6=>XLXN_8,
B7=>XLXN_9);
XLXI_9 : BOX_2
port map (A(7
downto 0)=>IN_02(7 downto 0),
B0=>XLXN_10,
B1=>XLXN_11,
B2=>XLXN_12,
B3=>XLXN_13,
B4=>XLXN_15,
B5=>XLXN_16,
B6=>XLXN_17,
B7=>XLXN_18);
XLXI_11 :
VECTOR_PATH
port map
(A0=>XLXN_23,
A1=>XLXN_24,
A2=>XLXN_25,
A3=>XLXN_26,
A4=>XLXN_27,
A5=>XLXN_28,
A6=>XLXN_29,
A7=>XLXN_30,
B(7
downto 0)=>OUT_1(7 downto 0));
end BEHAVIORAL;
--CODE FOR REG_PATH
library
IEEE;
use
IEEE.STD_LOGIC_1164.ALL;
use
IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity
REG_PATH is
Port ( DIN : in STD_LOGIC_VECTOR (07 downto
0):="00000000";
CLK : in STD_LOGIC;
RESETT : in STD_LOGIC;
DOUT : out STD_LOGIC_VECTOR (07 downto
0):="00000000");
end REG_PATH;
architecture
Behavioral of REG_PATH is
begin
process(CLK,RESETT,DIN)
begin
if
RESETT = '1' then
DOUT
<= "00000000";
elsif
CLK'event and CLK = '1' then
DOUT
<= DIN;
else
null;
end
if;
end
process;
end
Behavioral;
--SCHEMATIC FOR FOR SUMMATION OF 8 DOWN TO 1 .
--OUTPUT OF
SCHEMATIC
No comments:
Post a Comment