VHDL code for DATAPATH if else problem

TO DESIGN AND SIMULATE DEDICATED DATA PATH FOR SOLVING THE SIMPLE …IF THEN ELSE .. PROBLEM.

--CODE FOR REG_PATH

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity REG_PATH is

    Port ( D: in  STD_LOGIC_VECTOR(3 DOWNTO 0);

           CLK : in  STD_LOGIC;

           RESETT : in  STD_LOGIC;

           Q3,Q2,Q1,Q0 : OUT  STD_LOGIC);

end REG_PATH;

architecture Behavioral of REG_PATH is

begin

process(CLK,RESETT,D)

begin

if RESETT = '1' then

Q0<='0';

Q1<='0';

Q2<='0';

Q3<='0';

elsif CLK'event and CLK = '1' then

Q0<=D(0);

Q1<=D(1);

Q2<=D(2);

Q3<=D(3);

else 

null;

end if;

end process;

end Behavioral;

--CODE FOR MUX_PATH

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUX_PATH is

    Port ( IN1,IN2 : in  STD_LOGIC_VECTOR (03 downto 0);

           SEL : in  STD_LOGIC;

           OUTT : out  STD_LOGIC_VECTOR (03 downto 0));

end MUX_PATH;

architecture Behavioral of MUX_PATH is

begin

PROCESS(IN1,IN2,SEL)

BEGIN

IF SEL='1' THEN OUTT<= IN1;

ELSE OUTT<=IN2;

END IF;

END PROCESS;

end Behavioral;

--CODE FOR  REG_PATHH

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity REG_PATHH is

    Port ( D : in  STD_LOGIC_VECTOR (03 downto 0);

           CLK : in  STD_LOGIC;

           RESETT : in  STD_LOGIC;

           Q : out  STD_LOGIC_VECTOR (03 downto 0));

end REG_PATHH;

architecture Behavioral of REG_PATHH is

begin

process(CLK,RESETT,D)

begin 

if RESETT = '1' then

Q<="0000";

elsif CLK'event and CLK = '1' then

Q<=D;

else

null;

end if;

end process;

end Behavioral;

--SCHEMATIC FOR DATA_PATH_IF_ELSE

 

--OUTPUT OF  SCHEMATIC FOR DATA_PATH_IF_ELSE