Project Ideas

Project 1. FPGA based fast OMR (optical mask recognisation) sheet reader system

Description : OMR sheet is a paper with circle marks, one need to fill or darken the circles to select options. Mainly use to fill officials forms or to answer multiple choice questions. OMR sheets are use for fast and error less processing on user data.  FPGA is very powerful tool in real-time image processing. with FPGA it is possible to achieve processing on 30 OMR sheet per second.

System Requirements: 
a. Xilinx or Altera FPGA Board
b. Xilinx ISE or Altera quartus (Software development tool)
c. Camera (monochrome CMOS camera)
d. VGA monitor (Any PC monitor)

Project 2. FPGA based fast faulted product removal system ( example: removal of cracked soap from conveyor belt)

Description :  FPGAs have large number of input/output ports and hence can be very useful in automation system design. FPGA supports various industrial protocols and one can design his own protocol in FPGA.
By designing image edge detection system on FPGA, it is possible to detect cracks on Soap and then can be remove from conveyor belt. By using FPGA, processing on one image can be completed in 20 ms time and hence near about 20 sample of soap per second can be scan for defects.

System Requirements: 
a. Xilinx or Altera FPGA Board
b. Xilinx ISE or Altera quartus (Software development tool)
c. Camera (monochrome CMOS camera)
d. VGA monitor (Any PC monitor)


Project 3. FPGA based Robot control 

Description : FPGA based wireless control of robot system can be  used to for various application of military and industrial uses.

System Requirements: 
a. Xilinx or Altera FPGA Board
b. Xilinx ISE or Altera quartus (Software development tool)
c. Camera (monochrome CMOS camera)
d. zigbee wireless transmitter and receiver
  

VHDL code for register

--N-bit register with clear and load

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity reg is
generic(N : integer := 8);
port( load : in STD_LOGIC; a : in STD_LOGIC_VECTOR(N-1  downto 0);
clk : in STD_LOGIC; clr : in STD_LOGIC; b :out STD_LOGIC_VECTOR(N-1  downto 0));
end reg;

architecture reg of reg is
begin
process(clk, clr)
begin
if clr = '1' then
b <= (others=> '0');
elsif clk'event  and clk = '1' then
if load= '1' then
b<= a;
end if;
end if;
end process;
end reg;


output:

 

how to read content from text file and How to write content in text file in VHDL

--PROGRAM TO READ CONTENT FROM ONE FILE AND WRITE IT IN to ANOTHER FILE

--THIS PROGRAM HAS TO BE WRITTEN IN TESTBENCH MODULE

--INPUT AND OUTPUT text FILES SHOULD BE PRESENT IN YOUR PROJECT FOLDER

 

library ieee;

use ieee.std_logic_1164.all;

use STD.Textio.all;--PACKAGE CONTAIN FUNTIONS RELATED TO FILE READ/WRITE OPERATION

 

entity FA_TESTS is

end FA_TESTS;

architecture behavioral of FA_TESTS is

begin

 

process

file infile :text; --DEFINES INPUT FILE_HANDLE AND TYPE OF FILE

file outfile :text;--DEFINES INPUT FILE_HANDLE AND TYPE OF FILE

variable buff: line;--VARIABLE WITH TYPE LINE TO READ COMPLETE LINE/ROW AT A TIME

 

begin

file_open(infile,"gnc.txt",read_mode); --OPEN FILE NAME "GNC.TXT' TO READ CONTENT FROM THAT FILE

file_open(outfile,"gncc.txt", write_mode);--OPEN FILE NAME "GNCC.TXT" TO WRITE CONTENT TO THAT FILE

for i in 1 to 4 loop  --AS INPUT FILE "GNC.TXT" CONTAIN CONTENT OF 4 LINE

readline(infile, buff); --TO READ A LINE FROM INPUT FILE

writeline(outfile,buff);--TO WRITE A LINE TO OUTPUT FILE

end loop;

file_close(infile);--NECESSARY TO CLOSE OPEN FILE

file_close(outfile); --NECESSARY TO CLOSE OPEN FILE

wait;--TO HALT THE PROGRAM / TO AVOID INFINITE EXECUTION OF PROGRAM

end process;

 

end  behavioral;